1. Field of the Invention
The present invention relates to an array substrate for a transflective liquid crystal display device, and more particularly to a method for manufacturing an array substrate for a transflective liquid crystal display device including a transmission section having a transverse electric electrode and a reflection section having a vertical electric electrode, and having a structure in which electrodes making contact with an alignment layer may act as common electrodes.
2. Description of the Prior Art
Generally, liquid crystal display devices are operated with various driving modes. In order to drive such liquid crystal display devices, a plane switching alignment using a transverse electric field or a twisted nematic alignment using a vertical electric field has been widely used. However, such alignment structures may cause a ghost image. Electrification between an alignment layer and an organic layer aligned between an electrode and a liquid crystal has been mainly discussed as a reason for the ghost image. FIG. 1 is a view showing an induced polarization generated by a conventional transverse electrode structure. As shown in FIG. 1, a transverse electric field structure may generate a charge build-up effect, which creates a reverse electric field in left and right directions of an alignment layer. Thus, when a signal is changed, electric charges stacked on the alignment layer are not easily discharged to an exterior, causing a shielding and reinforcement phenomenon. Also, in a vertical electric field structure, an electric charge may be charged on alignment layers formed on upper and lower surfaces of a substrate different in such a manner that the electric charge charged on one alignment layer is different from the electric charge charged on the other alignment layer, so a potential difference is generated, also causing a shielding and reinforcement phenomenon. FIG. 2 is a view showing the shielding and reinforcement phenomenon caused by an alignment layer as a V-T curve of a TN mode. As shown in FIG. 2, such shielding and reinforcement action phenomenon may be maintained until the charge stacked on the alignment layer has been discharged in such a manner that a modified gradient curve shifted from an original gradient curve can be achieved. As is understood from FIG. 2, even though there is a great difference in desired gradient values, the real gradient is rarely changed, so the ghost image derived from an original image may occur. FIG. 3 is a view explaining a relationship between a distortion of a signal voltage caused by electric charges stacked on an alignment layer and a Feed-Through voltage. That is, as shown in FIG. 3 representing the distortion of the signal voltage applied to a liquid crystal layer, a drain voltage, which must be constantly applied to the liquid crystal layer, is dropped down, and then, is recovered due to the Feed-Through voltage Vp, thereby forming a transformation curve satisfying following equation 1.
                              V          p                =                              Cgd                                          C                ⁢                pixel                            +                              C                ⁢                storage                            +              Cgd                                ⁢          Δ          ⁢                                          ⁢          V                                    [                  Equation          ⁢                                          ⁢          1                ]            
Herein, Cpixel is a capacitance of a pixel, Cstorage is a capacitance of a common electrode, Cgd is a parasitic capacitance, and ΔVg=Vgh−Vgl.
If the Feed-Through voltage Vp is large, the flicker or the ghost image may be frequently created. Accordingly, in order to decrease the Feed-Through voltage Vp, studies for enlarging the size of the common electrode while reducing the parasitic capacitance have been variously researched. However, according to conventional designs for decreasing the Feed-Through voltage Vp, the common electrode is located below a pixel electrode, so that a charge-stacking phenomenon causing charges to be concentrated on an electrode section, may not be solved. In order to solve the above problem, changing the kind of alignment layer and the liquid crystal has been tried. However, such a method cannot completely solve the above problem. In order to solve the charge-stacking phenomenon, it is necessary to provide an electrode structure capable of minimizing an electric potential of electric charges, which are variously stacked in various positions according to the applied voltage. It is very disadvantageous for the electrode structure if the alignment layer and the liquid crystal are aligned between the common electrode and the pixel electrode.
If the pixel electrodes and common electrodes are aligned in series with a pole alignment pattern (+ − + − + −) in order to form the transverse electric field, electric charges having a reverse pole alignment pattern (− + − + − +) are stacked on alignment layers or films formed on the electrode. Also, if pixel electrodes and common electrodes are aligned with a predetermined pole alignment pattern (± ± ± ± ± ±) in order to form the vertical electric field, electric charges having a pole alignment pattern reverse to the predetermined pole alignment pattern (± ± ± ± ± ±) are stacked on the alignment layers. Such electric charges stacked on the alignment layers may create the Feed-Through voltage Vp, causing the ghost image. That is, the electric charges are differently formed in various positions because the electric charges may be charged according to an electrode alignment structure. FIG. 4 is a sectional view showing a conventional array substrate for a transflective liquid crystal display device.
Referring to FIG. 4, a source metal layer 3a and a drain metal layer 4a of a thin film transistor VII and a source metal layer 3b of a data pad unit are simultaneously formed on an upper surface of a substrate 1.
Then, amorphous silicon is deposited on the substrate 1, thereby forming a silicon layer (not shown). In addition, a first n+ amorphous silicon layer 2a is formed between the source metal layer 3a and the drain metal layer 4a of the thin film transistor and a second n+ amorphous silicon layer 2b, which is spaced by a predetermined distance from the source metal layer 3b of the data pad unit, is formed on a gate pad unit XI through etching the silicon layer. Then, an insulation material is coated on upper surfaces of the first n+ amorphous silicon layer 2a and the second n+ amorphous silicon layer 2b, thereby forming an insulation layer 6a of the thin film transistor and an insulation layer 6b of the gate pad unit. After that, a metal is coated on upper surfaces of the insulation layer 6a of the thin film transistor and the insulation layer 6b of the gate pad unit, thereby forming a gate metal layer 7a of the thin film transistor and a gate metal layer 7b of the gate pad unit XI. Also, an insulation layer 8 is formed on the substrate 1 on which the gate metal layer 7a of the thin film transistor and the gate metal layer 7b of the gate pad unit XI are formed.
Thereafter, a reflection plate 10 of the thin film transistor VII is formed. Also, an insulation layer 8′ is formed on the reflection plate 10. After that, a drain contact hole 11 exposing the drain metal layer 4a and a source contact hole 538 exposing the source metal layer 3b are formed by simultaneously patterning the insulation layer 8 and the insulation layer 8′. Reference number 12 is a via hole of a pad.
Even though the conventional array substrate utilizes a top gate manner, which may be applied to the present invention, a pixel electrode is located above a surface of a layer, thereby forming the ghost image. Also, the conventional array substrate has no light-shielding pattern, so it cannot shield light.